1. Field of the Invention
The present invention relates to an internal-voltage generating circuit and a semiconductor device including the same, and, more particularly relates to an internal-voltage generating circuit generating inside a chip thereof an internal voltage different from a power supply voltage supplied from outside, and a semiconductor device including the internal-voltage generating circuit.
2. Description of Related Art
A power supply voltage used in a semiconductor device such as a DRAM (Dynamic Random Access Memory) and the like has been reduced year by year, and power consumption has been also reduced accordingly. While a power supply voltage has been generally 5 V in the past, it has been reduced thereafter to 3.3 V, and a voltage of about 1.2 V is often used at present.
However, depending on a kind of a semiconductor device, there are internal circuits requiring a higher voltage than the power supply voltage. For example, in a DRAM, a selected word line is often set to a higher voltage than the power supply voltage. In this case, a boosted internal voltage is necessary in a word-line driving circuit. An internal-voltage generating circuit provided in the semiconductor device generates this internal voltage.
FIG. 16 is a block circuit showing one example of a semiconductor device including an internal-voltage generating circuit according to a related art.
A semiconductor device 10 shown in FIG. 16 includes an internal-voltage generating circuit 11 generating an internal voltage VPP by boosting a power supply voltage VDD, and an internal circuit 12 operated at the internal voltage VPP. With this arrangement, even when the power supply voltage VDD is set low, a higher internal voltage VPP can be supplied to the internal circuit 12.
However, in the semiconductor device 10 shown in FIG. 16, the internal-voltage generating circuit 11 continues generating the internal voltage VPP, regardless of whether the internal circuit 12 is in an active state. That is, even when the internal circuit 12 is in a standby state, the internal-voltage generating circuit 11 consumes power. Therefore, the semiconductor device 10 has a problem of consuming large power.
FIG. 17 is a block circuit showing another example of a semiconductor device including an internal-voltage generating circuit according to a related art.
A semiconductor device 20 shown in FIG. 17 has a P-channel MOS transistor 23 connected between a power source wiring supplied with the power supply voltage VDD and an internal-voltage generating circuit 21. A control signal 23a is supplied to a gate of the transistor 23. The control signal 23a becomes at a low level when the internal circuit 22 is in the active state, and becomes at a high level when the internal circuit 22 is in the standby state. Based on this configuration, a power supply to the internal-voltage generating circuit 21 is suspended during a period while the internal circuit 22 is in the standby state. Therefore, power consumption can be reduced more than that in the semiconductor device 10 shown in FIG. 16.
However, even when the transistor 23 is turned off, a predetermined off current IOFF flows. The off current IOFF greatly depends on a threshold voltage of the transistor 23. When the threshold voltage becomes higher, the off current IOFF becomes smaller, and when the threshold voltage becomes lower, the off current IOFF becomes larger. Therefore, when the power supply voltage VDD is high to some extent, the threshold voltage of the transistor 23 can be set high accordingly. Consequently, power consumption due to the off current IOFF does not become so problematic.
However, as described above, because the power supply voltage VDD has become lower in recent years, it is essential to use the transistor 23 having a lower threshold voltage. When the power supply voltage VDD becomes lower, the power consumption due to the off current IOFF increases, and the power reduction effect using the transistor 23 becomes small. Particularly, in the field where lower power consumption is important like products for mobile devices, power consumption due to the off current IOFF becomes a nonnegligible level.
Apart from the above, Japanese Patent Application Laid-open Nos. 2005-38502, 2005-71556, and 2006-180255 describe other techniques of reducing power consumption in a standby state.